Dell PowerEdge 1850 CPU socket - mystery solved

J. Epperson Dell at
Mon Oct 1 11:03:39 CDT 2007

On Mon, October 1, 2007 09:29, Kurt_Olsson at wrote:
> 1850 uses Netburst arch, not Core... 771/775 is only for Core (x) CPUs.
> Key Features of the Nocona / Irwindale Processor:
> Nocona processor utilizes 1MB L2 cache
> Irwindale processor utilizes 2MB L2 cache
> 604-pin PGA package in a ZIF socket
> FSB address will clock at 400MHz, and data at 800MHz.
> No termination required for non-populated CPUs (must populate CPU socket
> 1 first)
> Peak Bandwidth at 6.4 GB/s
> 64-byte Cache line size
> Data Inversion
> IOQ depth = 12
> Source -Synchronous Transfer (SST) 4x per bus clock
> Max trans per processor 29
> RISC/CISC hybrid architecture
> AGTL+ external bus
> Compatible with existing x86 code base
> Optimized for 32-bit code
> MMX support
> Streaming SIMD Extensions 2
> 64-bit Extensions

This is the second time in a week you've posted this exact text, without
elaboration, in response to messages that don't mention Netburst, Core,
771/775, Nocona, nor Irwindale.  I can make some inferences, but can you
elaborate on what point(s) you're trying to make?

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