Dell PowerEdge 1850 CPU socket - mystery solved

Kurt_Olsson at Kurt_Olsson at
Mon Oct 1 08:29:01 CDT 2007

1850 uses Netburst arch, not Core... 771/775 is only for Core (x) CPUs.

Key Features of the Nocona / Irwindale Processor:

Nocona processor utilizes 1MB L2 cache 
Irwindale processor utilizes 2MB L2 cache 
604-pin PGA package in a ZIF socket 
FSB address will clock at 400MHz, and data at 800MHz. 
No termination required for non-populated CPUs (must populate CPU socket
1 first) 
Peak Bandwidth at 6.4 GB/s 
64-byte Cache line size 
Data Inversion 
IOQ depth = 12 
Source -Synchronous Transfer (SST) 4x per bus clock 
Max trans per processor 29 
RISC/CISC hybrid architecture 
AGTL+ external bus 
Compatible with existing x86 code base 
Optimized for 32-bit code 
MMX support 
Streaming SIMD Extensions 2 
64-bit Extensions

-----Original Message-----
From: linux-poweredge-bounces at
[mailto:linux-poweredge-bounces at] On Behalf Of Marcus Bointon
Sent: Sunday, September 30, 2007 6:22 PM
To: linux-poweredge-Lists
Subject: Dell PowerEdge 1850 CPU socket - mystery solved

After a bit of server disembowelment I finally have a definitive  
answer: Poweredge 1850 and 1950 have completely different CPU  
sockets. The 1850 uses a PGA socket with some unknown number of pins,  
and the 1950 uses an LGA (no pins). Nowhere in the Dell server docs  
have I found this documented! Hopefully this will help someone else  
that is wondering about this.

Marcus Bointon
Synchromedia Limited: Creators of
UK resellers of info at hand CRM solutions
marcus at |

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