megaraid_sas xscale interrupt mask?

Joe Malicki jmalicki at
Mon Jan 8 09:59:33 CST 2007

Hi Sumant,

Thanks for the quick response!  I don't believe we're having any issues
with the mask - we're just trying to debug some issues we're
having with some controllers with, and that's the only
real semantic difference (other than crashdump mode) between
RHEL 4 kernels and, and it spooked me that the changelog
didn't mention that it was intentional... I really appreciate the
response, it helps us eliminate possibilities and doubt.


Patro, Sumant wrote:
> Hello Joe,
> 	The mask value 0x1f is to mask out interrupts. The value in the
> current kernel code is appropriate for all controllers that the driver
> supports. 
> 	Are you seeing any specific issue in driver with this mask
> value?
> Regards,
> Sumant 
> -----Original Message-----
> From: Joe Malicki [mailto:jmalicki at] 
> Sent: Wednesday, January 03, 2007 5:41 PM
> To: Patro, Sumant
> Cc: linux-poweredge at; Keith R. Baker; linux-scsi at
> Subject: megaraid_sas xscale interrupt mask?
> Hi Sumant,
> While trying to debug Dell PERC 5/i RAID controller problems we've been
> having with the megaraid_sas driver, we've been inspecting differences
> between the Red Hat EL 4 kernel (which Dell officially supports) versus
> the stock Linux driver we use.  We found a very interesting
> change, introduced into linux 2.6.16, that seems very odd to us:
> d09bafd2d/cbbe2a30b8c2eb94?lnk=st&q=outbound_intr_mask+0x1f+0x00000001&r
> num=1#cbbe2a30b8c2eb94
> The title of the thread is "megaraid_sas: new template defined to
> represent each type of controllers", and introduces this curious change:
>  /**
>   * megasas_disable_intr -      Disables interrupts
>   * @regs:                      MFI register set
>   */
>  static inline void
>  megasas_disable_intr(struct megasas_register_set __iomem * regs)  {
> -       u32 mask = readl(&regs->outbound_intr_mask) & (~0x00000001);
> +       u32 mask = 0x1f;
>         writel(mask, &regs->outbound_intr_mask);
>         /* Dummy readl to force pci flush */
> Interrupts are enabled by writing "1" to the same register.
> Is there a specific reason for this?  Is it possible that Dell PERC 5/i
> controllers differ from LSI controllers in this respect?  It seems odd
> that this change would be introduced without any explanation for what
> it's meant to do, so I am very curious if it could be an inadvertently
> introduced bug that is causing some problems.
> Thanks!
> Joe Malicki

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