timer interrupts not SMP?
dhubbard at dino.hostasaurus.com
Tue Apr 30 14:27:00 CDT 2002
My new 1650 running 2.4.9-31enterprise seems to favor
cpu0 by 2:1 but is not all on cpu0. My older 2400
servers are all cpu0... :-) Maybe a function of
the chipset? What chipset do your other balanced
> -----Original Message-----
> From: rwotten at checkfree.com [mailto:rwotten at checkfree.com]
> Sent: Tuesday, April 30, 2002 3:03 PM
> To: linux-poweredge at dell.com
> Subject: timer interrupts not SMP?
> On my 2.2.20 kernel on my PowerEdge 2550's I can do the following:
> # cat /proc/interrupts
> $ cat /proc/interrupts
> CPU0 CPU1
> 0: 51810494 0 XT-PIC timer
> 1: 27 37 IO-APIC-edge keyboard
> 2: 0 0 XT-PIC
> 12: 0 0 IO-APIC-edge
> PS/2 Mouse
> 13: 1 0 XT-PIC
> 14: 9 6 IO-APIC-edge ide0
> 16: 1684300 1735100 IO-APIC-level eth0
> 17: 254 364 IO-APIC-level eth1
> 30: 14 16 IO-APIC-level aic7xxx
> 31: 94473 95809 IO-APIC-level aacraid
> NMI: 0
> ERR: 0
> It shows the interrupts for a number of system components.
> All of them are pretty balanced between the two CPU's except
> the "timer"
> interrupts, which on my Dell servers are 100% on CPU0.
> On other non-Dell servers (with pretty much the same kernel) the timer
> interrupts are balanced between the two CPU's.
> I doubt it makes much difference, but I am curious as to why
> this might be.
> Rick Otten
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